For increasing the operating speed and reducing the power consumption, the circuitry of an integrated circuit (IC) chip usually comprises transistors that withstand low voltages. For example, the IC chip comprises 1.8V transistors.
Since an output pad of the IC chip provides a higher output voltage (e.g., 3.3V), the 1.8V transistors of the I/O circuit are in a cascade connection.
For example, in the I/O circuit, two P-type transistors in the cascade connection are connected between a power voltage (3.3V) and the output pad. If the I/O circuit provides 0V to the output pad, the source-drain voltages of the P-type transistors are within the withstanding voltage range (i.e., 1.8V).
Similarly, in the I/O circuit, two N-type transistors in the cascade connection are connected between the output pad and a ground voltage (GND). If the I/O circuit provides 3.3V to the output pad, the source-drain voltages of the N-type transistors are within the withstanding voltage range (i.e., 1.8V.)
However, the conventional I/O circuit still has some drawbacks. For example, it is necessary to properly control the gate voltages of the P-type transistors or the N-type transistors. If the gate voltages are not properly controlled, the gate-source voltages of the transistors are possibly beyond the withstanding voltage range and thus the transistors are burnt out.